The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions. The MOS transistor can be used as a semiconductor memory device if some mechanism is available to adjust the threshold voltage (the minimum control voltage necessary to allow current to flow through the channel). A high threshold voltage represents one memory state while a low threshold voltage represents the opposite memory state.
One form of semiconductor memory is a nonvolatile memory in which the memory state of a memory cell is determined by whether or not an electrical charge is stored on a charge storage layer built into the gate structure of a field effect transistor. To enhance the storage capacity of such a nonvolatile memory, two storage nodes can be built into each memory cell. The storage nodes are associated with locations in the charge storage layer at opposite sides of the gate structure. As the capacity of semiconductor memories increases, the size of each individual device that is used to implement the memory shrinks in size. With a memory that uses dual storage nodes per memory cell, the reduction in device size means that the spacing between the two storage nodes of a memory cell decreases. As the spacing between storage nodes decreases, problems arise with respect to the reliability and retention of the memory data. If a single continuous charge storage layer is used for both memory nodes, charge stored in one memory node can leak through the charge storage layer to the other memory node of the memory bit to corrupt the memory stored at that other memory node. Additionally, as device size decreases, programming of one memory node can disturb the data stored in the other memory node due to relatively wide charge distributions in the charge storage layer. Still further, as device sizes decrease, the spacing between bit lines associated with the two memory nodes decreases leading to possible problems with punch through between the bit lines. Such problems limit the possible choices for erasing such dual bit memory cells.
Accordingly, it is desirable to provide a semiconductor memory device having physically split charge storage nodes and to provide methods for its fabrication. In addition, it is desirable to provide a method for fabricating a dual charge storage semiconductor memory device that avoids bit line punch through and allows erasing by Fowler-Nordheim tunneling. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.